1. Field of the Invention (Technical Field)
The present invention relates generally to the field of rendering the luminance values for the pixels of a display from an analog video signal. More specifically, the present invention relates to techniques for correctly rendering display pixels from an analog source for a high-resolution image without compromising the image resolution and without introducing dynamic display anomalies.
2. Background Art
Although analog interfaces have traditionally been employed for transmitting video to display systems, the quality of high-resolution images, particularly of computer-generated images, can be degraded when transmitted over an analog interface. Although image quality can be preserved by employing a digital interface, an analog interface is often required or preferred for reasons of cost and/or compatibility.
In order to display images from an analog video signal on a flat-panel display, such as an AMLCD-based display, the analog video input must be periodically sampled and converted into digital values with an Analog-to-Digital (A-to-D) converter circuit. The clock input to the A-to-D converter is generated from a Phase-Locked-Loop (PLL) circuit that synchronizes this clock to the horizontal synchronization signal in the analog video input. The video input is generally passed through an analog low-pass filter prior to the A-to-D conversion in order to attenuate higher frequency components in the video signal. Sometimes a low-pass digital FIR filter is also employed on the sampled digital data stream to further limit the spatial bandwidth of the displayed image. Although such a limitation in the spatial bandwidth may be acceptable when displaying images from some video sources, this can significantly reduce the sharpness of the displayed image.
Analog interfaces have recently been employed to display high-resolution computer-generated images. In these applications the video signal includes legitimate high-frequency components, including edges with transitions in brightness and/or color that occur over the distance of a single pixel or that may be precisely aligned with the boundary between adjacent pixels. An attenuation of these higher frequencies then compromises image quality by extending the spatial regions over which these video transitions occur.
It is theoretically possible to recover a high-resolution image from an analog input by deriving the amplitude level for each pixel of the input signal with a single sample from the A-to-D converter. Ideally, each of these samples would then occur very near the center of the time-period during which the video amplitude level is stable for the input pixel, but this requires a precise and consistent timing alignment between the sampling clock and the analog video input. However, the individual circuit components in the PLL have unit-to-unit variations in their propagation delay times, additional variations with temperature, and changes that result from the aging of the components over their lifetime. All of these tolerances can combine to cause a significant misalignment between the phase of the sampling clock and the video input. The video input has a specified time-delay from horizontal sync to the start of the first pixel, and this time-delay must, of course, also include a tolerance. Moreover, the sampling clock generated by the PLL circuitry also has inherent jitter and an inherent phase drift over the horizontal cycle time.
The combination of all these tolerances can result in a phase error between the input video signal and the sampling clock that is large enough so that a pixel could be rendered by a sample that occurs during the transition time between pixels, instead of during the stable time-period of the pixel. If the jitter on the sampling clock is then comparable in magnitude to the video transition time (i.e., to the signal rise and fall times), a pixel could be rendered with significantly different values on different display refresh cycles. This can result in very objectionable dynamic artifacts whereby individual pixels, and groups of pixels, will periodically change their brightness level and/or their color as the phase relationship between the video input and the sampling clock changes. Although the severity of these dynamic display artifacts could be reduced by low-pass filtering, it has already been noted that this would lower image quality by decreasing image sharpness.
A variable delay can be included in the circuit path of one of the two inputs to the phase comparator of the PLL circuit (or it can be put in series with the sample clock) in order to adjust the average phase offset between the input video signal and the sample clock. This adjustment could correct for long-term phase errors, such as out-of-tolerance components, but not for short-term phase changes, such as jitter and drift on the sample clock. A variable delay circuit can be implemented, for example, by passing a signal through a low-pass filter (to increase the rise and fall time) followed by an analog comparator circuit. By changing the value of a threshold voltage at the other input to the comparator, the delay time of a signal transition through this circuit can be adjusted, thereby controlling the phase offset between the sample clock and the video input.
U.S. Pat. No. 6,317,005 (Morel et al.) shows a variable delay in the horizontal sync input to the phase detector of a PLL (designated in their FIG. 8 as a “LAG CIRCUIT”) in order to adjust the phase of the A-to-D sample clock by means of a feedback loop that detects the relative phase of the video transitions. As previously noted, this approach only provides for an adjustment of the average phase offset over the long term and it does not address the issues of phase jitter and drift on the sample clock. The Morel invention also employs a mix of both analog and digital in the circuit path of the feedback loop, and the analog components contribute to a significant tolerance range on the resulting, albeit controlled, phase offset. Thus, for applications that require a precise phase alignment, this circuit may require a calibration procedure.
U.S. Pat. No. 6,323,910 (Clark) employs a “delay generator” circuit, but it does not use this to adjust the phase of the sample clock. The Clark invention does not address the issues of aligning the phase of the sample clock to the input pixels of the analog video signal or of achieving any specific phase alignment to the horizontal sync. Instead, it discloses a method for achieving a consistent phase alignment to the horizontal sync over the multiple horizontal cycles of the video signal.
A circuit that would accurately render high-resolution images from an analog video signal without introducing dynamic display artifacts and that would automatically adjust for both short-term and long-term phase errors between the sample clock and the video input would be of great benefit. It would also be beneficial if this circuit did not require any calibration adjustments. It would be of additional benefit if this were an exclusively digital circuit instead of a mix of analog and digital, as this would provide a more cost-effective circuit.